In conventional transistor-transistor logic (TTL) and diode-transistor logic (DTL) devices, logical values corresponding to binary "1" and "0" are ordinarily represented at the output by a high level voltage V.sub.oh, for example greater than 2.4 volts, and a low level voltage V.sub.ol, for example less than 0.8 volts. In positive logic, the high level binary "1" is derived from a voltage source V.sub.cc which "sources" the current to the output when a binary "1" is to be delivered by the output gate. When a binary "0" is required at the output, the output gate blocks sourcing current and instead "sinks" the current from the output load to ground so that the low level voltage V.sub.ol appears at the output of the logic gate. Thus, the typical TTL output gate functions by "sourcing" and "sinking" current at the output according to whether a binary "1" (high level voltage) or a binary "0" (low level voltage) is the desired outcome of previously executed logical operations. In negative logic the representation of binary 1 and 0 by high and low level voltage is reversed.
A conventional low power Schottky TTL output device is illustrated in FIG. 1. Several elements or stages can be identified in such a TTL output gate. The "pullup" element for sourcing current from the higher level voltage V.sub.cc and delivering binary 1 consists of transistors Q4 and Q5 forming a Darlington transistor pair that can supply a relatively large current between the high level voltage source V.sub.cc and the output V.sub.o when a much smaller current is applied to the base of Q4. The "pulldown" element or stage for sinking current and voltage from the output to ground consists of transistor Q2 with conventional squaring network at its base comprised of resistors R6 and R7 and transistor Q6. The phase splitter element or stage consists of transistor Q1 which receives the data signal input to the gate in the form of a high or low level voltage at V.sub.i and controls the pullup and pulldown elements for either sourcing or sinking current at the output V.sub.o as determined by the data signal input to the gate.
When a low level voltage or potential appears at the input V.sub.i, a low voltage also appears at the base of phase splitter transistor Q1 and this transistor is deprived of base drive current so that it no longer conducts current through its collector to emitter thereby turning off pulldown transistor Q2. Ideally, the output V.sub.o of the gate is therefore isolated from ground. At the same time, because Q1 is non-conducting, the high level voltage V.sub.cc appears at the base of sourcing transistor Q4 supplying base current for transistor Q4 to conduct to the base of Q5 which in turn becomes conducting and "sources" current from V.sub.cc to the output V.sub.o. The TTL logic gate is therefore inherently inverting as a binary 0 at the input V.sub.i represented by a low voltage level generates a binary 1 at the output represented by voltage level V.sub.oh.
When a binary 1 appears at the input, current from R1 supplies base drive to transistor Q1, Q1 becomes conducting, sinking current from the base of Q4 and therefore turning off the Darlington transistor current source represented by transistors Q4 and Q5. Current from high level voltage V.sub.cc is therefore no longer sourced to the output. At the same time, pulldown transistor Q2 becomes conducting through its collector to emitter to ground as a result of the current applied to its base and begins to discharge current from whatever load capacitance may be coupled to the output V.sub.o of the gate, bringing the output V.sub.o to a low level potential corresponding to binary 0. The output load is mainly capacitive.
As shown in FIG. 1 and in later figures, some of the transistor and diode components are typically Schottky diodes and transistors indicated by the opposite square hooks in the schematic symbols. The Schottky clamping effected by an internal modification in these devices produces quicker turnoff during switching. A transistor logic output gate of the type illustrated in FIG. 1, however, suffers the disadvantage of high power consumption and retarded switching during transition from low to high potential at the output as hereafter described.
The problem addressed by the present invention arises during this transition from low to high level voltage at the output in state of the art transistor logic output devices such as that illustrated in FIG. 1. In the ideal situation during low to high transition at the output, the pulldown element transistor Q2 would turn off completely before a large current begins to flow from the pullup element Darlington transistor current source into the load capacitance. In the actual case, the pulldown element is turning off and the pullup element is turning on over a period of time with overlap so that some of the pullup current flows through the pulldown element to ground instead of into the load capacitance. One result is wasteful consumption of power.
The reason that pulldown element transistor Q2 does not turn off completely is because of the occurrence of parasitic feedback capacitance in transistors, primarily the capacitance associated with the base-collector junction. Since pulldown transistor Q2 is required to conduct large amounts of current in sinking current from the load, it is physically larger than most of the transistors in the circuit and thus has a large base-collector capacitance. The equivalent circuit showing the effect of this base-collector junction capacitance on transistor Q2 is illustrated in FIGS. 1A and 1B where the equivalent feedback capacitance accompanying the junction is shown as C.sub.bc connected across the base and collector of transistor Q2. This relatively large base to collector junction capacitance C.sub.bc in the pulldown element transistor is known as the "Miller capacitance." When the voltage or potential at the output is rising, a significant amount of current i.sub.bc is generated proportional to the rate of change of voltage across the base collector capacitance C.sub.bc. This current is also referred to as the "Miller current." Some of this Miller current flows into the base of Q2 designated in FIGS. 1A and 1B as i.sub.b which base current is then multiplied by the gain .beta. of the transistor Q2 resulting in a large collector current i.sub.c =.beta..sub.ib from Q2. This large current to ground diverts current from the pullup element reducing its effectiveness in charging up the load capacitance. As a result, there is wasteful power consumption and retardation or delay in the turnoff of pulldown element transistor Q2.
For further insight into the problem reference is made to the squaring network of FIG. 1 coupled between the base of pulldown transistor Q2 and ground. The squaring network, consisting of transistor Q6 and resistors R6 and R7, is so named because its function is to square off the transition characteristics of the pulldown transistor. It also is called the "lag circuit" because it stays on a little longer than transistors Q1 and Q2 during transition from low to high at the output when Q1 and Q2 are turning off. When Q2 is conducting, a small current passes through the squaring network saturating Q6. R7 must be large to limit the current flow away from the base of Q2 so that Q2 will not significantly be deprived of base current during the time when Q2 must conduct large current through its collector from the output. When Q1 and Q2 are turning off, R7 and Q6 pull current out of the base of Q2 to turn it off quickly.
The value of resistance R7 must therefore be a tradeoff. It must pass enough current to square off the transition characteristics at the pulldown element. On the other hand, it must still be a large resistance, large enough to restrict current loss to ground so that current to the base of Q2 is not drained or sunk when Q2 is trying to conduct and provide low potential at the output.
It is also frequently the case in conventional TTL and DTL transistor logic output devices that instead of a squaring network, a resistance R7 alone is used coupled between the base of pulldown transistor Q2 and ground to facilitate turn off to Q2 during transition. Similarly, such resistance must be large and in that respect similar to R7 so the discussion here is also applicable.
The impact of this limitation of the squaring network of FIG. 1 and of the pulldown element base to ground turnoff resistance R7 in some conventional transistor logic output devices is presented with reference to FIG. 1B. The objective during transition from low to high potential at the output is to turn off Q2 completely and quickly before the Darlington transistor current source pullup element begins to conduct. Because of the Miller capacitance and Miller current, and because of the high resistance limitations on the squaring network or pulldown transistor base turn off resistance, this is not possible in the conventional circuits of the type illustrated by way of example in FIG. 1. The Miller capacitance C.sub.bc is always present at the base collector junction and cannot be eliminated. As shown in FIG. 1B for positive changing voltage during transition from low to high potential at the output current is generated and flows back across C.sub.bc in the form of the Miller current i.sub.bc. This Miller current divides, one portion flowing through the squaring network resistance or the base to ground resistance R7, this portion designated i.sub.r. The other portion flows into the base of pulldown transistor Q2 and is designated i.sub.b. This portion i.sub.b of the Miller current is multiplied by the gain of transistor Q2 so that Q2 will not turn off but continue to conduct current while the pullup element is trying to deliver current to the output. The result as described above is wasteful power consumption and delay in transition.
It is apparent that the current i.sub.b flowing into the base of Q2 must be eliminated to avoid the harmful effects of the Miller current. This base feedback current i.sub.b equals i.sub.bc -i.sub.r, that is the Miller current minus the portion diverted through resistance R7, and this could only be done if i.sub.r were equal to or greater than the Miller current i.sub.cb. However, this condition that i.sub.r be greater than or equal to the Miller current cannot be achieved in the conventional circuits of FIGS. 1 and 2 because resistance R7 must have such a large value for the reasons heretofore described. Q2 will therefore stay on until the voltage at the output stops changing from low to high because the Miller current across the Miller capacitance is proportional to the rate of change of potential across it. During this time, considerable current passes to ground from the pullup element through the amplified collector current of the still conducting pulldown transistor, wasting power.